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checkevent
mir
llvmint
The
llvm.xcore.checkevent
intrinsic.
version(LDC && xcore)
@
safe
pure nothrow @
nogc
pragma(
LDC_intrinsic
, "llvm.xcore.checkevent")
i8
*
checkevent
(
i8
*
)
Meta
Source
See Implementation
mir
llvmint
functions
_int
aesni_aesdec
aesni_aesdeclast
aesni_aesenc
aesni_aesenclast
aesni_aesimc
aesni_aeskeygenassist
avx_addsub_pd_256
avx_addsub_ps_256
avx_max_pd_256
avx_max_ps_256
avx_min_pd_256
avx_min_ps_256
avx_rcp_ps_256
avx_round_pd_256
avx_round_ps_256
avx_rsqrt_ps_256
avx_sqrt_pd_256
avx_sqrt_ps_256
pclmulqdq
rdpmc
rdtsc
rdtscp
sse2_add_sd
sse2_clflush
sse2_cmp_pd
sse2_cmp_sd
sse2_comieq_sd
sse2_comige_sd
sse2_comigt_sd
sse2_comile_sd
sse2_comilt_sd
sse2_comineq_sd
sse2_cvtdq2pd
sse2_cvtdq2ps
sse2_cvtpd2dq
sse2_cvtpd2ps
sse2_cvtps2dq
sse2_cvtps2pd
sse2_cvtsd2si
sse2_cvtsd2si64
sse2_cvtsd2ss
sse2_cvtsi2sd
sse2_cvtsi642sd
sse2_cvtss2sd
sse2_cvttpd2dq
sse2_cvttps2dq
sse2_cvttsd2si
sse2_cvttsd2si64
sse2_div_sd
sse2_lfence
sse2_maskmov_dqu
sse2_max_pd
sse2_max_sd
sse2_mfence
sse2_min_pd
sse2_min_sd
sse2_movmsk_pd
sse2_mul_sd
sse2_packssdw_128
sse2_packsswb_128
sse2_packuswb_128
sse2_padds_b
sse2_padds_w
sse2_paddus_b
sse2_paddus_w
sse2_pause
sse2_pavg_b
sse2_pavg_w
sse2_pmadd_wd
sse2_pmaxs_w
sse2_pmaxu_b
sse2_pmins_w
sse2_pminu_b
sse2_pmovmskb_128
sse2_pmulh_w
sse2_pmulhu_w
sse2_pmulu_dq
sse2_psad_bw
sse2_pshuf_d
sse2_pshufh_w
sse2_pshufl_w
sse2_psll_d
sse2_psll_dq
sse2_psll_dq_bs
sse2_psll_q
sse2_psll_w
sse2_pslli_d
sse2_pslli_q
sse2_pslli_w
sse2_psra_d
sse2_psra_w
sse2_psrai_d
sse2_psrai_w
sse2_psrl_d
sse2_psrl_dq
sse2_psrl_dq_bs
sse2_psrl_q
sse2_psrl_w
sse2_psrli_d
sse2_psrli_q
sse2_psrli_w
sse2_psubs_b
sse2_psubs_w
sse2_psubus_b
sse2_psubus_w
sse2_sqrt_pd
sse2_sqrt_sd
sse2_storel_dq
sse2_storeu_dq
sse2_storeu_pd
sse2_sub_sd
sse2_ucomieq_sd
sse2_ucomige_sd
sse2_ucomigt_sd
sse2_ucomile_sd
sse2_ucomilt_sd
sse2_ucomineq_sd
sse3_addsub_pd
sse3_addsub_ps
sse3_hadd_pd
sse3_hadd_ps
sse3_hsub_pd
sse3_hsub_ps
sse3_ldu_dq
sse3_monitor
sse3_mwait
sse41_blendpd
sse41_blendps
sse41_blendvpd
sse41_blendvps
sse41_dppd
sse41_dpps
sse41_extractps
sse41_insertps
sse41_movntdqa
sse41_mpsadbw
sse41_packusdw
sse41_pblendvb
sse41_pblendw
sse41_pextrb
sse41_pextrd
sse41_pextrq
sse41_phminposuw
sse41_pmaxsb
sse41_pmaxsd
sse41_pmaxud
sse41_pmaxuw
sse41_pminsb
sse41_pminsd
sse41_pminud
sse41_pminuw
sse41_pmovsxbd
sse41_pmovsxbq
sse41_pmovsxbw
sse41_pmovsxdq
sse41_pmovsxwd
sse41_pmovsxwq
sse41_pmovzxbd
sse41_pmovzxbq
sse41_pmovzxbw
sse41_pmovzxdq
sse41_pmovzxwd
sse41_pmovzxwq
sse41_pmuldq
sse41_ptestc
sse41_ptestnzc
sse41_ptestz
sse41_round_pd
sse41_round_ps
sse41_round_sd
sse41_round_ss
sse42_crc32_32_16
sse42_crc32_32_32
sse42_crc32_32_8
sse42_crc32_64_64
sse42_pcmpestri128
sse42_pcmpestria128
sse42_pcmpestric128
sse42_pcmpestrio128
sse42_pcmpestris128
sse42_pcmpestriz128
sse42_pcmpestrm128
sse42_pcmpistri128
sse42_pcmpistria128
sse42_pcmpistric128
sse42_pcmpistrio128
sse42_pcmpistris128
sse42_pcmpistriz128
sse42_pcmpistrm128
sse4a_extrq
sse4a_extrqi
sse4a_insertq
sse4a_insertqi
sse4a_movnt_sd
sse4a_movnt_ss
sse_add_ss
sse_cmp_ps
sse_cmp_ss
sse_comieq_ss
sse_comige_ss
sse_comigt_ss
sse_comile_ss
sse_comilt_ss
sse_comineq_ss
sse_cvtsi2ss
sse_cvtsi642ss
sse_cvtss2si
sse_cvtss2si64
sse_cvttss2si
sse_cvttss2si64
sse_div_ss
sse_ldmxcsr
sse_max_ps
sse_max_ss
sse_min_ps
sse_min_ss
sse_movmsk_ps
sse_mul_ss
sse_rcp_ps
sse_rcp_ss
sse_rsqrt_ps
sse_rsqrt_ss
sse_sfence
sse_sqrt_ps
sse_sqrt_ss
sse_stmxcsr
sse_storeu_ps
sse_sub_ss
sse_ucomieq_ss
sse_ucomige_ss
sse_ucomigt_ss
sse_ucomile_ss
sse_ucomilt_ss
sse_ucomineq_ss
ssse3_pabs_b_128
ssse3_pabs_d_128
ssse3_pabs_w_128
ssse3_phadd_d_128
ssse3_phadd_sw_128
ssse3_phadd_w_128
ssse3_phsub_d_128
ssse3_phsub_sw_128
ssse3_phsub_w_128
ssse3_pmadd_ub_sw_128
ssse3_pmul_hr_sw_128
ssse3_pshuf_b_128
ssse3_psign_b_128
ssse3_psign_d_128
ssse3_psign_w_128
The llvm.xcore.checkevent intrinsic.