1 /++ 2 $(H2 Common information for all x86 and x86_64 vendors.) 3 4 $(GREEN This module is compatible with betterC compilation mode.) 5 6 Note: 7 `T.max` value value is used to represent fully-associative Cache/TLB. 8 9 References: 10 $(LINK2 https://en.wikipedia.org/wiki/CPUID, wikipedia:CPUID) 11 12 License: $(WEB www.boost.org/LICENSE_1_0.txt, Boost License 1.0). 13 14 Authors: Ilia Ki 15 +/ 16 module cpuid.x86_any; 17 18 version(LDC) 19 { 20 import ldc.llvmasm; 21 // @@@FIXME@@@ 22 // https://github.com/ldc-developers/druntime/pull/80 23 pragma(LDC_inline_asm) 24 { 25 template __asmtuple(T...) 26 { 27 __asmtuple_t!(T) __asmtuple(const(char)[] asmcode, const(char)[] constraints, ...) pure nothrow @nogc; 28 } 29 } 30 } 31 32 version(X86) 33 version = X86_Any; 34 else 35 version(X86_64) 36 version = X86_Any; 37 38 version(X86_Any): 39 40 version(D_InlineAsm_X86) 41 version = InlineAsm_X86_Any; 42 else 43 version(D_InlineAsm_X86_64) 44 version = InlineAsm_X86_Any; 45 46 public import cpuid.common; 47 48 /// Leaf0 49 private immutable uint _maxBasicLeaf; 50 51 /// Leaf1 52 private immutable Leaf1Information leaf1Information; 53 /// Leaf7 54 private immutable Leaf7Information leaf7Information; 55 56 /// ExtLeaf0 57 private immutable uint _maxExtendedLeaf; 58 59 /// Other 60 private immutable VendorIndex _vendorId; 61 private immutable VendorIndex _virtualVendorId; 62 63 /++ 64 Initialize basic x86 CPU information. 65 It is safe to call this function multiple times. 66 +/ 67 export extern(C) 68 nothrow @nogc 69 void mir_cpuid_x86_any_init() 70 { 71 import cpuid.unified: _mut; 72 static if (__VERSION__ >= 2068) 73 pragma(inline, false); 74 CpuInfo info = void; 75 76 info = _cpuid(0); 77 _maxBasicLeaf._mut = info.a; 78 79 { 80 uint[3] n = void; 81 n[0] = info.b; 82 n[1] = info.d; 83 n[2] = info.c; 84 _vendorId._mut = VendorIndex.undefined; 85 auto vs = vendors[0 .. $ - 1]; 86 foreach(i, ref name; (cast(uint[3]*)(vs.ptr))[0 .. vs.length]) 87 { 88 if (n[0] == name[0] && n[1] == name[1] && n[2] == name[2]) 89 { 90 _vendorId._mut = cast(VendorIndex) i; 91 break; 92 } 93 } 94 } 95 _virtualVendorId._mut = _vendorId; 96 leaf1Information._mut.info = _cpuid(1); 97 if(_maxBasicLeaf >= 7) 98 leaf7Information._mut.info = _cpuid(0x07); 99 if(leaf1Information.virtual) 100 { 101 auto infov = _cpuid(0x4000_0000); 102 uint[3] n = void; 103 n[0] = infov.b; 104 n[1] = infov.c; 105 n[2] = infov.d; 106 _virtualVendorId._mut = VendorIndex.undefinedvm; 107 auto vs = vendors[VendorIndex.undefined + 1 .. $ - 1]; 108 foreach(i, ref name; (cast(uint[3]*)(vs.ptr))[0 .. vs.length]) 109 { 110 if (n[0] == name[0] && n[1] == name[1] && n[2] == name[2]) 111 { 112 _virtualVendorId._mut = cast(VendorIndex) (i + VendorIndex.undefined + 1); 113 break; 114 } 115 } 116 } 117 _maxExtendedLeaf._mut = _cpuid(0x8000_0000).a; 118 } 119 120 /// Basic information about CPU. 121 union Leaf1Information 122 { 123 import mir.bitmanip: bitfields; 124 /// CPUID payload 125 CpuInfo info; 126 struct 127 { 128 @trusted @property pure nothrow @nogc: 129 version(D_Ddoc) 130 { 131 const: 132 /// Stepping ID 133 uint stepping(); 134 /// Model 135 uint model(); 136 /// Family ID 137 uint family(); 138 /// Processor Type, Specification: Intel 139 uint type(); 140 /// Extended Model ID 141 uint extendedModel(); 142 /// Extended Family ID 143 uint extendedFamily(); 144 145 146 /// Brand Index 147 ubyte brandIndex; 148 /// `clflush` line size 149 ubyte clflushLineSize; 150 /// maximal number of logical processors 151 ubyte maxLogicalProcessors; 152 /// initial APIC 153 ubyte initialAPIC; 154 155 /// SSE3 Extensions 156 bool sse3(); 157 /// Carryless Multiplication 158 bool pclmulqdq(); 159 /// 64-bit DS Area 160 bool dtes64(); 161 /// MONITOR/MWAIT 162 bool monitor(); 163 ///(); /// CPL Qualified Debug Store 164 bool ds_cpl(); 165 /// Virtual Machine Extensions 166 bool vmx(); 167 /// Safer Mode Extensions 168 bool smx(); 169 /// Enhanced Intel SpeedStep® Technology 170 bool eist(); 171 /// Thermal Monitor 2 172 bool therm_monitor2(); 173 /// SSSE3 Extensions 174 bool ssse3(); 175 /// L1 Context ID 176 bool cnxt_id(); 177 /// 178 bool sdbg(); 179 /// Fused Multiply Add 180 bool fma(); 181 /// 182 bool cmpxchg16b(); 183 /// TPR Update Control 184 bool xtpr(); 185 /// Perf/Debug Capability MSR xTPR Update Control 186 bool pdcm(); 187 /// Process-context Identifiers 188 bool pcid(); 189 /// Direct Cache Access 190 bool dca(); 191 /// SSE4.1 192 bool sse41(); 193 /// SSE4.2 194 bool sse42(); 195 /// 196 bool x2apic(); 197 /// 198 bool movbe(); 199 /// 200 bool popcnt(); 201 /// 202 bool tsc_deadline(); 203 /// 204 bool aes(); 205 /// 206 bool xsave(); 207 /// 208 bool osxsave(); 209 /// 210 bool avx(); 211 /// 212 bool f16c(); 213 /// 214 bool rdrand(); 215 /// 216 bool virtual(); 217 /// x87 FPU on Chip 218 bool fpu(); 219 /// Virtual-8086 Mode Enhancement 220 bool vme(); 221 /// Debugging Extensions 222 bool de(); 223 /// Page Size Extensions 224 bool pse(); 225 /// Time Stamp Counter 226 bool tsc(); 227 /// RDMSR and WRMSR Support 228 bool msr(); 229 /// Physical Address Extensions 230 bool pae(); 231 /// Machine Check Exception 232 bool mce(); 233 /// CMPXCHG8B Inst. 234 bool cx8(); 235 /// APIC on Chip 236 bool apic(); 237 /// SYSENTER and SYSEXIT 238 bool sep(); 239 /// Memory Type Range Registers 240 bool mtrr(); 241 /// PTE Global Bit 242 bool pge(); 243 /// Machine Check Architecture 244 bool mca(); 245 /// Conditional Move/Compare Instruction 246 bool cmov(); 247 /// Page Attribute Table 248 bool pat(); 249 /// Page Size Extension 250 bool pse36(); 251 /// Processor Serial Number 252 bool psn(); 253 /// CLFLUSH instruction 254 bool clfsh(); 255 /// Debug Store 256 bool ds(); 257 /// Thermal Monitor and Clock Ctrl 258 bool acpi(); 259 /// MMX Technology 260 bool mmx(); 261 /// FXSAVE/FXRSTOR 262 bool fxsr(); 263 /// SSE Extensions 264 bool sse(); 265 /// SSE2 Extensions 266 bool sse2(); 267 /// Self Snoop 268 bool self_snoop(); 269 /// Multi-threading 270 bool htt(); 271 /// Therm. Monitor 272 bool therm_monitor(); 273 /// Pend. Brk. EN. 274 bool pbe(); 275 } 276 else 277 { 278 /// EAX 279 mixin(bitfields!( 280 uint, "stepping", 3 - 0 + 1, /// Stepping ID 281 uint, "model", 7 - 4 + 1, /// Model 282 uint, "family", 11 - 8 + 1, /// Family ID 283 uint, "type", 13 - 12 + 1, /// Processor Type, Specification: Intel 284 uint, "", 15 - 14 + 1, 285 uint, "extendedModel", 19 - 16 + 1, /// Extended Model ID 286 uint, "extendedFamily", 27 - 20 + 1, /// Extended Family ID 287 uint, "", 31 - 28 + 1, 288 )); 289 290 /// EBX 291 ubyte brandIndex; 292 ubyte clflushLineSize; 293 ubyte maxLogicalProcessors; 294 ubyte initialAPIC; 295 296 /// ECX 297 mixin(bitfields!( 298 bool, "sse3", 1, /// SSE3 Extensions 299 bool, "pclmulqdq", 1, /// Carryless Multiplication 300 bool, "dtes64", 1, /// 64-bit DS Area 301 bool, "monitor", 1, /// MONITOR/MWAIT 302 bool, "ds_cpl", 1, /// CPL Qualified Debug Store 303 bool, "vmx", 1, /// Virtual Machine Extensions 304 bool, "smx", 1, /// Safer Mode Extensions 305 bool, "eist", 1, /// Enhanced Intel SpeedStep® Technology 306 bool, "therm_monitor2", 1, /// Thermal Monitor 2 307 bool, "ssse3", 1, /// SSSE3 Extensions 308 bool, "cnxt_id", 1, /// L1 Context ID 309 bool, "sdbg", 1, 310 bool, "fma", 1, /// Fused Multiply Add 311 bool, "cmpxchg16b", 1, 312 bool, "xtpr", 1, /// TPR Update Control 313 bool, "pdcm", 1, /// Perf/Debug Capability MSR xTPR Update Control 314 bool, "", 1, 315 bool, "pcid", 1, /// Process-context Identifiers 316 bool, "dca", 1, /// Direct Cache Access 317 bool, "sse41", 1, /// SSE4.1 318 bool, "sse42", 1, /// SSE4.2 319 bool, "x2apic", 1, 320 bool, "movbe", 1, 321 bool, "popcnt", 1, 322 bool, "tsc_deadline", 1, 323 bool, "aes", 1, 324 bool, "xsave", 1, 325 bool, "osxsave", 1, 326 bool, "avx", 1, 327 bool, "f16c", 1, 328 bool, "rdrand", 1, 329 bool, "virtual", 1, 330 )); 331 332 /// EDX 333 mixin(bitfields!( 334 bool, "fpu", 1, /// x87 FPU on Chip 335 bool, "vme", 1, /// Virtual-8086 Mode Enhancement 336 bool, "de", 1, /// Debugging Extensions 337 bool, "pse", 1, /// Page Size Extensions 338 bool, "tsc", 1, /// Time Stamp Counter 339 bool, "msr", 1, /// RDMSR and WRMSR Support 340 bool, "pae", 1, /// Physical Address Extensions 341 bool, "mce", 1, /// Machine Check Exception 342 bool, "cx8", 1, /// CMPXCHG8B Inst. 343 bool, "apic", 1, /// APIC on Chip 344 bool, "", 1, 345 bool, "sep", 1, /// SYSENTER and SYSEXIT 346 bool, "mtrr", 1, /// Memory Type Range Registers 347 bool, "pge", 1, /// PTE Global Bit 348 bool, "mca", 1, /// Machine Check Architecture 349 bool, "cmov", 1, /// Conditional Move/Compare Instruction 350 bool, "pat", 1, /// Page Attribute Table 351 bool, "pse36", 1, /// Page Size Extension 352 bool, "psn", 1, /// Processor Serial Number 353 bool, "clfsh", 1, /// CLFLUSH instruction 354 bool, "", 1, 355 bool, "ds", 1, /// Debug Store 356 bool, "acpi", 1, /// Thermal Monitor and Clock Ctrl 357 bool, "mmx", 1, /// MMX Technology 358 bool, "fxsr", 1, /// FXSAVE/FXRSTOR 359 bool, "sse", 1, /// SSE Extensions 360 bool, "sse2", 1, /// SSE2 Extensions 361 bool, "self_snoop", 1, /// Self Snoop 362 bool, "htt", 1, /// Multi-threading 363 bool, "therm_monitor", 1, /// Therm. Monitor 364 bool, "", 1, 365 bool, "pbe", 1, /// Pend. Brk. EN. 366 )); 367 } 368 } 369 } 370 371 /// ditto 372 alias cpuid_x86_any_init = mir_cpuid_x86_any_init; 373 374 /// Extended information about CPU. 375 union Leaf7Information 376 { 377 import mir.bitmanip: bitfields; 378 /// CPUID payload 379 CpuInfo info; 380 struct 381 { 382 /// Reports the maximum input value for supported leaf 7 sub-leaves 383 uint max7SubLeafs; 384 @trusted @property pure nothrow @nogc: 385 version(D_Ddoc) 386 { 387 const: 388 /// Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1. 389 bool fsgsbase(); 390 ///MSR is supported if 1. 391 bool ia32_tsc_adjust(); 392 /// Supports Intel® Software Guard Extensions (Intel® SGX Extensions) if 1. 393 bool sgx(); 394 /// Bit Manipulation Instruction Set 1 395 bool bmi1(); 396 /// Transactional Synchronization Extensions 397 bool hle(); 398 /// Advanced Vector Extensions 2 399 bool avx2(); 400 /// x87 FPU Data Pointer updated only on x87 exceptions if 1. 401 bool fdp_excptn_only(); 402 /// Supports Supervisor-Mode Execution Prevention if 1. 403 bool smep(); 404 /// Bit Manipulation Instruction Set 2 405 bool bmi2(); 406 /// Enhanced REP MOVSB/STOSB if 1. 407 bool supports(); 408 /// If 1, supports INVPCID instruction for system software that manages process-context identifiers. 409 bool invpcid(); 410 /// Transactional Synchronization Extensions 411 bool rtm(); 412 /// Supports Intel® Resource Director Technology (Intel® RDT) Monitoring capability if 1. 413 bool rdt_m(); 414 ///FPU CS and FPU DS values if 1. 415 bool deprecates(); 416 /// Supports Intel® Memory Protection Extensions if 1. 417 bool mpx(); 418 /// Supports Intel® Resource Director Technology (Intel® RDT) Allocation capability if 1. 419 bool rdt_a(); 420 /// AVX-512 Foundation 421 bool avx512f(); 422 /// AVX-512 Doubleword and Quadword Instructions 423 bool avx512dq(); 424 /// RDSEED instruction 425 bool rdseed(); 426 /// Intel ADX (Multi-Precision Add-Carry Instruction Extensions) 427 bool adx(); 428 /// Supports Supervisor-Mode Access Prevention (and the CLAC/STAC instructions) if 1. 429 bool smap(); 430 /// AVX-512 Integer Fused Multiply-Add Instructions 431 bool avx512ifma(); 432 /// PCOMMIT instruction 433 bool pcommit(); 434 /// CLFLUSHOPT instruction 435 bool clflushopt(); 436 /// CLWB instruction 437 bool clwb(); 438 /// Intel Processor Trace. 439 bool intel_pt(); 440 /// AVX-512 Prefetch Instructions 441 bool avx512pf(); 442 /// AVX-512 Exponential and Reciprocal Instructions 443 bool avx512er(); 444 /// AVX-512 Conflict Detection Instructions 445 bool avx512cd(); 446 /// supports Intel® Secure Hash Algorithm Extens 447 bool sha(); 448 /// AVX-512 Byte and Word Instructions 449 bool avx512bw(); 450 /// AVX-512 Vector Length Extensions 451 bool avx512vl(); 452 /// PREFETCHWT1 instruction 453 bool prefetchwt1(); 454 /// AVX-512 Vector Bit Manipulation Instructions 455 bool avx512vbmi(); 456 /// Supports user-mode instruction prevention if 1 457 bool umip(); 458 /// Memory Protection Keys for User-mode pages 459 bool pku(); 460 /// If 1, OS has set CR4.PKE to enable protection keys (and the RDPKRU/WRPKRU instructions). 461 bool ospke(); 462 /// 463 bool waitpkg(); 464 /// 465 bool avx512vbmi2(); 466 /// Supports CET shadow stack features if 1. 467 bool cet_ss(); 468 /// 469 bool gfni(); 470 /// 471 bool vaes(); 472 /// 473 bool vpclmulqdq(); 474 /// 475 bool avx512vnni(); 476 /// 477 bool avx512bitalg(); 478 /// 479 bool avx512vpopcntdq(); 480 /// The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-bit mode. 481 uint mawau(); 482 /// RDPID and IA32_TSC_AUX are available if 1. 483 bool rdpid(); 484 /// Supports cache line demote if 1. 485 bool cldemote(); 486 /// Supports MOVDIRI if 1. 487 bool movdiri(); 488 /// Supports MOVDIR64B if 1. 489 bool movdir64b(); 490 /// Supports SGX Launch Configuration if 1. 491 bool sgx_lc(); 492 } 493 else 494 { 495 mixin(bitfields!( 496 bool, "fsgsbase", 1, /// Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1. 497 bool, "ia32_tsc_adjust", 1, ///MSR is supported if 1. 498 bool, "sgx", 1, /// Supports Intel® Software Guard Extensions (Intel® SGX Extensions) if 1. 499 bool, "bmi1", 1, /// Bit Manipulation Instruction Set 1 500 bool, "hle", 1, /// Transactional Synchronization Extensions 501 bool, "avx2", 1, /// Advanced Vector Extensions 2 502 bool, "fdp_excptn_only", 1, /// x87 FPU Data Pointer updated only on x87 exceptions if 1. 503 bool, "smep", 1, /// Supports Supervisor-Mode Execution Prevention if 1. 504 bool, "bmi2", 1, /// Bit Manipulation Instruction Set 2 505 bool, "supports", 1, /// Enhanced REP MOVSB/STOSB if 1. 506 bool, "invpcid", 1, /// If 1, supports INVPCID instruction for system software that manages process-context identifiers. 507 bool, "rtm", 1, /// Transactional Synchronization Extensions 508 bool, "rdt_m", 1, /// Supports Intel® Resource Director Technology (Intel® RDT) Monitoring capability if 1. 509 bool, "deprecates", 1, ///FPU CS and FPU DS values if 1. 510 bool, "mpx", 1, /// Supports Intel® Memory Protection Extensions if 1. 511 bool, "rdt_a", 1, /// Supports Intel® Resource Director Technology (Intel® RDT) Allocation capability if 1. 512 bool, "avx512f", 1, /// AVX-512 Foundation 513 bool, "avx512dq", 1, /// AVX-512 Doubleword and Quadword Instructions 514 bool, "rdseed", 1, /// RDSEED instruction 515 bool, "adx", 1, /// Intel ADX (Multi-Precision Add-Carry Instruction Extensions) 516 bool, "smap", 1, /// Supports Supervisor-Mode Access Prevention (and the CLAC/STAC instructions) if 1. 517 bool, "avx512ifma", 1, /// AVX-512 Integer Fused Multiply-Add Instructions 518 bool, "pcommit", 1, /// PCOMMIT instruction 519 bool, "clflushopt", 1, /// CLFLUSHOPT instruction 520 bool, "clwb", 1, /// CLWB instruction 521 bool, "intel_pt", 1, /// Intel Processor Trace. 522 bool, "avx512pf", 1, /// AVX-512 Prefetch Instructions 523 bool, "avx512er", 1, /// AVX-512 Exponential and Reciprocal Instructions 524 bool, "avx512cd", 1, /// AVX-512 Conflict Detection Instructions 525 bool, "sha", 1, /// supports Intel® Secure Hash Algorithm Extens 526 bool, "avx512bw", 1, /// AVX-512 Byte and Word Instructions 527 bool, "avx512vl", 1, /// AVX-512 Vector Length Extensions 528 )); 529 mixin(bitfields!( 530 bool, "prefetchwt1", 1, /// PREFETCHWT1 instruction 531 bool, "avx512vbmi", 1, /// AVX-512 Vector Bit Manipulation Instructions 532 bool, "umip", 1, /// Supports user-mode instruction prevention if 1 533 bool, "pku", 1, /// Memory Protection Keys for User-mode pages 534 bool, "ospke", 1, // If 1, OS has set CR4.PKE to enable protection keys (and the RDPKRU/WRPKRU instructions). 535 bool, "waitpkg", 1, /// 536 bool, "avx512vbmi2", 1, /// 537 bool, "cet_ss", 1, /// Supports CET shadow stack features if 1. 538 bool, "gfni", 1, /// 539 bool, "vaes", 1, /// 540 bool, "vpclmulqdq", 1, /// 541 bool, "avx512vnni", 1, /// 542 bool, "avx512bitalg", 1, /// 543 bool, "", 1, 544 bool, "avx512vpopcntdq", 1, /// 545 uint, "", 16 - 15 + 1, 546 uint, "mawau", 21 - 17 + 1, /// The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-bit mode. 547 bool, "rdpid", 1, /// RDPID and IA32_TSC_AUX are available if 1. 548 uint, "", 24 - 23 + 1, 549 bool, "cldemote", 1, /// Supports cache line demote if 1. 550 bool, "", 1, 551 bool, "movdiri", 1, /// Supports MOVDIRI if 1. 552 bool, "movdir64b", 1, /// Supports MOVDIR64B if 1. 553 bool, "", 1, 554 bool, "sgx_lc", 1, /// Supports SGX Launch Configuration if 1. 555 bool, "", 1, 556 )); 557 } 558 } 559 } 560 561 562 563 /// x86 CPU information 564 struct CpuInfo 565 { 566 /// EAX 567 uint a; 568 /// EBX 569 uint b; 570 /// ECX 571 uint c; 572 /// EDX 573 uint d; 574 } 575 576 /++ 577 Params: 578 eax = function id 579 ecx = sub-function id 580 +/ 581 pure nothrow @nogc @trusted 582 CpuInfo _cpuid()(uint eax, uint ecx = 0) 583 { 584 uint a = void; 585 uint b = void; 586 uint c = void; 587 uint d = void; 588 version(LDC) 589 { 590 pragma(inline, true); 591 auto asmt = __asmtuple! 592 (uint, uint, uint, uint) ( 593 "cpuid", 594 "={eax},={ebx},={ecx},={edx},{eax},{ecx}", 595 eax, ecx); 596 a = asmt.v[0]; 597 b = asmt.v[1]; 598 c = asmt.v[2]; 599 d = asmt.v[3]; 600 } 601 else 602 version(GNU) 603 asm pure nothrow @nogc 604 { 605 "cpuid" : 606 "=a" a, 607 "=b" b, 608 "=c" c, 609 "=d" d, 610 : "a" eax, "c" ecx; 611 } 612 else 613 version(InlineAsm_X86_Any) 614 asm pure nothrow @nogc 615 { 616 mov EAX, eax; 617 mov ECX, ecx; 618 cpuid; 619 mov a, EAX; 620 mov b, EBX; 621 mov c, ECX; 622 mov d, EDX; 623 } 624 else static assert(0); 625 return CpuInfo(a, b, c, d); 626 } 627 628 nothrow @nogc @property: 629 630 align(4) 631 private __gshared immutable char[12][22] _vendors = 632 [ 633 "GenuineIntel", 634 "AuthenticAMD", 635 636 " SiS SiS SiS", 637 " UMC UMC UMC", 638 " VIA VIA VIA", 639 "AMDisbetter!", 640 "CentaurHauls", 641 "CyrixInstead", 642 "HygonGenuine", 643 "GenuineTMx86", 644 "Geode by NSC", 645 "NexGenDriven", 646 "RiseRiseRise", 647 "TransmetaCPU", 648 "Vortex86 SoC", 649 " undefined", 650 651 " KVM KVM KVM", 652 " lrpepyh vr", 653 "Microsoft Hv", 654 "VMwareVMware", 655 "XenVMMXenVMM", 656 "undefined vm", 657 ]; 658 659 /// VendorIndex name 660 immutable(char)[12][] vendors()() 661 { 662 return _vendors; 663 } 664 665 /// 666 unittest 667 { 668 assert(vendors[VendorIndex.intel] == "GenuineIntel"); 669 } 670 671 /// VendorIndex encoded value. 672 VendorIndex vendorIndex()() 673 { 674 return _vendorId; 675 } 676 677 /// VendorIndex encoded value for virtual machine. 678 VendorIndex virtualVendorIndex()() 679 { 680 return _virtualVendorId; 681 } 682 683 /// Maximum Input Value for Basic CPUID Information 684 uint maxBasicLeaf()() 685 { 686 return _maxBasicLeaf; 687 } 688 689 /// Maximum Input Value for Extended CPUID Information 690 uint maxExtendedLeaf()() 691 { 692 return _maxExtendedLeaf; 693 } 694 695 /// Reports the maximum input value for supported leaf 7 sub-leaves. 696 uint max7SubLeafs()() 697 { 698 return leaf7Information.max7SubLeafs; 699 } 700 701 /// Encoded vendors 702 enum VendorIndex 703 { 704 /// Intel 705 intel, 706 /// AMD 707 amd, 708 709 /// SiS 710 sis, 711 /// UMC 712 umc, 713 /// VIA 714 via, 715 /// early engineering samples of AMD K5 processor 716 amd_old, 717 /// Centaur (Including some VIA CPU) 718 centaur, 719 /// Cyrix 720 cyrix, 721 /// Hygon CPU (AMD like) 722 hygon, 723 /// Transmeta 724 transmeta, 725 /// National Semiconductor 726 nsc, 727 /// NexGen 728 nexgen, 729 /// Rise 730 rise, 731 /// Transmeta 732 transmeta_old, 733 /// Vortex 734 vortex, 735 736 /// undefined 737 undefined, 738 739 740 /// KVM 741 kvm, 742 /// Parallels 743 parallels, 744 /// Microsoft Hyper-V or Windows Virtual PC 745 microsoft, 746 /// VMware 747 vmware, 748 /// Xen HVM 749 xen, 750 751 /// undefined virtual machine 752 undefinedvm, 753 } 754 755 /++ 756 Brand, e.g. `Intel(R) Core(TM) i7-4770HQ CPU @ 2.20GHz`. 757 Returns: brand length 758 Params: brand = fixed length string to initiate 759 +/ 760 size_t brand()(ref char[48] brand) 761 { 762 static if (__VERSION__ >= 2068) 763 pragma(inline, false); 764 CpuInfo info = void; 765 info = _cpuid(0 + 2 ^ 0x8000_0000); 766 (cast(uint[12])brand)[0 * 4 + 0] = info.a; 767 (cast(uint[12])brand)[0 * 4 + 1] = info.b; 768 (cast(uint[12])brand)[0 * 4 + 2] = info.c; 769 (cast(uint[12])brand)[0 * 4 + 3] = info.d; 770 info = _cpuid(1 + 2 ^ 0x8000_0000); 771 (cast(uint[12])brand)[1 * 4 + 0] = info.a; 772 (cast(uint[12])brand)[1 * 4 + 1] = info.b; 773 (cast(uint[12])brand)[1 * 4 + 2] = info.c; 774 (cast(uint[12])brand)[1 * 4 + 3] = info.d; 775 info = _cpuid(2 + 2 ^ 0x8000_0000); 776 (cast(uint[12])brand)[2 * 4 + 0] = info.a; 777 (cast(uint[12])brand)[2 * 4 + 1] = info.b; 778 (cast(uint[12])brand)[2 * 4 + 2] = info.c; 779 (cast(uint[12])brand)[2 * 4 + 3] = info.d; 780 781 size_t i = brand.length; 782 while(brand[i - 1] == '\0') 783 { 784 --i; 785 if(i == 0) 786 break; 787 } 788 return i; 789 } 790 791 /++ 792 Vendor, e.g. `GenuineIntel`. 793 +/ 794 string vendor()() 795 { 796 return vendors[_vendorId]; 797 } 798 799 /++ 800 Virtual vendor, e.g. `GenuineIntel` or `VMwareVMware`. 801 +/ 802 string virtualVendor()() 803 { 804 return vendors[_virtualVendorId]; 805 } 806 807 /++ 808 Brand Index 809 +/ 810 ubyte brandIndex()() { return leaf1Information.brandIndex; } 811 /++ 812 CLFLUSH line size 813 Note: Value ∗ 8 = cache line size in bytes; used also by CLFLUSHOPT. 814 +/ 815 ubyte clflushLineSize()() { return leaf1Information.clflushLineSize; } 816 /++ 817 Maximum number of addressable IDs for logical processors in this physical package. 818 +/ 819 ubyte maxLogicalProcessors()() { return leaf1Information.maxLogicalProcessors; } 820 /++ 821 Initial APIC ID 822 +/ 823 ubyte initialAPIC()() { return leaf1Information.initialAPIC; } 824 /// Stepping ID 825 uint stepping()() { return leaf1Information.stepping; } 826 /// Model 827 uint model()() { return leaf1Information.model; } 828 /// Family ID 829 uint family()() { return leaf1Information.family; } 830 /// Processor Type, Specification: Intel 831 uint type()() { return leaf1Information.type; } 832 /// Extended Model ID 833 uint extendedModel()() { return leaf1Information.extendedModel; } 834 /// Extended Family ID 835 uint extendedFamily()() { return leaf1Information.extendedFamily; } 836 /// SSE3 Extensions 837 bool sse3()() { return leaf1Information.sse3; } 838 /// Carryless Multiplication 839 bool pclmulqdq()() { return leaf1Information.pclmulqdq; } 840 /// 64-bit DS Area 841 bool dtes64()() { return leaf1Information.dtes64; } 842 /// MONITOR/MWAIT 843 bool monitor()() { return leaf1Information.monitor; } 844 /// CPL Qualified Debug Store 845 bool ds_cpl()() { return leaf1Information.ds_cpl; } 846 /// Virtual Machine Extensions 847 bool vmx()() { return leaf1Information.vmx; } 848 /// Safer Mode Extensions 849 bool smx()() { return leaf1Information.smx; } 850 /// Enhanced Intel SpeedStep® Technology 851 bool eist()() { return leaf1Information.eist; } 852 /// Thermal Monitor 2 853 bool therm_monitor2()() { return leaf1Information.therm_monitor2; } 854 /// SSSE3 Extensions 855 bool ssse3()() { return leaf1Information.ssse3; } 856 /// L1 Context ID 857 bool cnxt_id()() { return leaf1Information.cnxt_id; } 858 /// 859 bool sdbg()() { return leaf1Information.sdbg; } 860 /// Fused Multiply Add 861 bool fma()() { return leaf1Information.fma; } 862 /// 863 bool cmpxchg16b()() { return leaf1Information.cmpxchg16b; } 864 /// TPR Update Control 865 bool xtpr()() { return leaf1Information.xtpr; } 866 /// Perf/Debug Capability MSR xTPR Update Control 867 bool pdcm()() { return leaf1Information.pdcm; } 868 /// Process-context Identifiers 869 bool pcid()() { return leaf1Information.pcid; } 870 /// Direct Cache Access 871 bool dca()() { return leaf1Information.dca; } 872 /// SSE4.1 873 bool sse41()() { return leaf1Information.sse41; } 874 /// SSE4.2 875 bool sse42()() { return leaf1Information.sse42; } 876 /// 877 bool x2apic()() { return leaf1Information.x2apic; } 878 /// 879 bool movbe()() { return leaf1Information.movbe; } 880 /// 881 bool popcnt()() { return leaf1Information.popcnt; } 882 /// 883 bool tsc_deadline()() { return leaf1Information.tsc_deadline; } 884 /// 885 bool aes()() { return leaf1Information.aes; } 886 /// 887 bool xsave()() { return leaf1Information.xsave; } 888 /// 889 bool osxsave()() { return leaf1Information.osxsave; } 890 /// 891 bool avx()() { return leaf1Information.avx; } 892 /// 893 bool f16c()() { return leaf1Information.f16c; } 894 /// 895 bool rdrand()() { return leaf1Information.rdrand; } 896 /// Virtual machine 897 bool virtual()() { return leaf1Information.virtual; } 898 /// x87 FPU on Chip 899 bool fpu()() { return leaf1Information.fpu; } 900 /// Virtual-8086 Mode Enhancement 901 bool vme()() { return leaf1Information.vme; } 902 /// Debugging Extensions 903 bool de()() { return leaf1Information.de; } 904 /// Page Size Extensions 905 bool pse()() { return leaf1Information.pse; } 906 /// Time Stamp Counter 907 bool tsc()() { return leaf1Information.tsc; } 908 /// RDMSR and WRMSR Support 909 bool msr()() { return leaf1Information.msr; } 910 /// Physical Address Extensions 911 bool pae()() { return leaf1Information.pae; } 912 /// Machine Check Exception 913 bool mce()() { return leaf1Information.mce; } 914 /// CMPXCHG8B Inst. 915 bool cx8()() { return leaf1Information.cx8; } 916 /// APIC on Chip 917 bool apic()() { return leaf1Information.apic; } 918 /// SYSENTER and SYSEXIT 919 bool sep()() { return leaf1Information.sep; } 920 /// Memory Type Range Registers 921 bool mtrr()() { return leaf1Information.mtrr; } 922 /// PTE Global Bit 923 bool pge()() { return leaf1Information.pge; } 924 /// Machine Check Architecture 925 bool mca()() { return leaf1Information.mca; } 926 /// Conditional Move/Compare Instruction 927 bool cmov()() { return leaf1Information.cmov; } 928 /// Page Attribute Table 929 bool pat()() { return leaf1Information.pat; } 930 /// Page Size Extension 931 bool pse36()() { return leaf1Information.pse36; } 932 /// Processor Serial Number 933 bool psn()() { return leaf1Information.psn; } 934 /// CLFLUSH instruction 935 bool clfsh()() { return leaf1Information.clfsh; } 936 /// Debug Store 937 bool ds()() { return leaf1Information.ds; } 938 /// Thermal Monitor and Clock Ctrl 939 bool acpi()() { return leaf1Information.acpi; } 940 /// MMX Technology 941 bool mmx()() { return leaf1Information.mmx; } 942 /// FXSAVE/FXRSTOR 943 bool fxsr()() { return leaf1Information.fxsr; } 944 /// SSE Extensions 945 bool sse()() { return leaf1Information.sse; } 946 /// SSE2 Extensions 947 bool sse2()() { return leaf1Information.sse2; } 948 /// Self Snoop 949 bool self_snoop()() { return leaf1Information.self_snoop; } 950 /// Multi-threading 951 bool htt()() { return leaf1Information.htt; } 952 /// Therm. Monitor 953 bool therm_monitor()() { return leaf1Information.therm_monitor; } 954 /// Pend. Brk. EN. 955 bool pbe()() { return leaf1Information.pbe; } 956 957 // EXTENDED 7 958 959 /// Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1. 960 bool fsgsbase()() { return leaf7Information.fsgsbase; } 961 ///MSR is supported if 1. 962 bool ia32_tsc_adjust()() { return leaf7Information.ia32_tsc_adjust; } 963 /// Supports Intel® Software Guard Extensions (Intel® SGX Extensions) if 1. 964 bool sgx()() { return leaf7Information.sgx; } 965 /// Bit Manipulation Instruction Set 1 966 bool bmi1()() { return leaf7Information.bmi1; } 967 /// Transactional Synchronization Extensions 968 bool hle()() { return leaf7Information.hle; } 969 /// Advanced Vector Extensions 2 970 bool avx2()() { return leaf7Information.avx2; } 971 /// x87 FPU Data Pointer updated only on x87 exceptions if 1. 972 bool fdp_excptn_only()() { return leaf7Information.fdp_excptn_only; } 973 /// Supports Supervisor-Mode Execution Prevention if 1. 974 bool smep()() { return leaf7Information.smep; } 975 /// Bit Manipulation Instruction Set 2 976 bool bmi2()() { return leaf7Information.bmi2; } 977 /// Enhanced REP MOVSB/STOSB if 1. 978 bool supports()() { return leaf7Information.supports; } 979 /// If 1, supports INVPCID instruction for system software that manages process-context identifiers. 980 bool invpcid()() { return leaf7Information.invpcid; } 981 /// Transactional Synchronization Extensions 982 bool rtm()() { return leaf7Information.rtm; } 983 /// Supports Intel® Resource Director Technology (Intel® RDT) Monitoring capability if 1. 984 bool rdt_m()() { return leaf7Information.rdt_m; } 985 ///FPU CS and FPU DS values if 1. 986 bool deprecates()() { return leaf7Information.deprecates; } 987 /// Supports Intel® Memory Protection Extensions if 1. 988 bool mpx()() { return leaf7Information.mpx; } 989 /// Supports Intel® Resource Director Technology (Intel® RDT) Allocation capability if 1. 990 bool rdt_a()() { return leaf7Information.rdt_a; } 991 /// AVX-512 Foundation 992 bool avx512f()() { return leaf7Information.avx512f; } 993 /// AVX-512 Doubleword and Quadword Instructions 994 bool avx512dq()() { return leaf7Information.avx512dq; } 995 /// RDSEED instruction 996 bool rdseed()() { return leaf7Information.rdseed; } 997 /// Intel ADX (Multi-Precision Add-Carry Instruction Extensions) 998 bool adx()() { return leaf7Information.adx; } 999 /// Supports Supervisor-Mode Access Prevention (and the CLAC/STAC instructions) if 1. 1000 bool smap()() { return leaf7Information.smap; } 1001 /// AVX-512 Integer Fused Multiply-Add Instructions 1002 bool avx512ifma()() { return leaf7Information.avx512ifma; } 1003 /// PCOMMIT instruction 1004 bool pcommit()() { return leaf7Information.pcommit; } 1005 /// CLFLUSHOPT instruction 1006 bool clflushopt()() { return leaf7Information.clflushopt; } 1007 /// CLWB instruction 1008 bool clwb()() { return leaf7Information.clwb; } 1009 /// Intel Processor Trace. 1010 bool intel_pt()() { return leaf7Information.intel_pt; } 1011 /// AVX-512 Prefetch Instructions 1012 bool avx512pf()() { return leaf7Information.avx512pf; } 1013 /// AVX-512 Exponential and Reciprocal Instructions 1014 bool avx512er()() { return leaf7Information.avx512er; } 1015 /// AVX-512 Conflict Detection Instructions 1016 bool avx512cd()() { return leaf7Information.avx512cd; } 1017 /// supports Intel® Secure Hash Algorithm Extens 1018 bool sha()() { return leaf7Information.sha; } 1019 /// AVX-512 Byte and Word Instructions 1020 bool avx512bw()() { return leaf7Information.avx512bw; } 1021 /// AVX-512 Vector Length Extensions 1022 bool avx512vl()() { return leaf7Information.avx512vl; } 1023 /// PREFETCHWT1 instruction 1024 bool prefetchwt1()() { return leaf7Information.prefetchwt1; } 1025 /// AVX-512 Vector Bit Manipulation Instructions 1026 bool avx512vbmi()() { return leaf7Information.avx512vbmi; } 1027 /// Supports user-mode instruction prevention if 1 1028 bool umip()() { return leaf7Information.umip; } 1029 /// Memory Protection Keys for User-mode pages 1030 bool pku()() { return leaf7Information.pku; } 1031 /// If 1, OS has set CR4.PKE to enable protection keys (and the RDPKRU/WRPKRU instructions). 1032 bool ospke()() { return leaf7Information.ospke; } 1033 /// 1034 bool waitpkg()() { return leaf7Information.waitpkg; } 1035 /// 1036 bool avx512vbmi2()() { return leaf7Information.avx512vbmi2; } 1037 /// Supports CET shadow stack features if 1. 1038 bool cet_ss()() { return leaf7Information.cet_ss; } 1039 /// 1040 bool gfni()() { return leaf7Information.gfni; } 1041 /// 1042 bool vaes()() { return leaf7Information.vaes; } 1043 /// 1044 bool vpclmulqdq()() { return leaf7Information.vpclmulqdq; } 1045 /// 1046 bool avx512vnni()() { return leaf7Information.avx512vnni; } 1047 /// 1048 bool avx512bitalg()() { return leaf7Information.avx512bitalg; } 1049 /// 1050 bool avx512vpopcntdq()() { return leaf7Information.avx512vpopcntdq; } 1051 /// The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-bit mode. 1052 uint mawau()() { return leaf7Information.mawau; } 1053 /// RDPID and IA32_TSC_AUX are available if 1. 1054 bool rdpid(); 1055 /// Supports cache line demote if 1. 1056 bool cldemote()() { return leaf7Information.cldemote; } 1057 /// Supports MOVDIRI if 1. 1058 bool movdiri()() { return leaf7Information.movdiri; } 1059 /// Supports MOVDIR64B if 1. 1060 bool movdir64b()() { return leaf7Information.movdir64b; } 1061 /// Supports SGX Launch Configuration if 1. 1062 bool sgx_lc()() { return leaf7Information.sgx_lc; }