Basic information about CPU.
Encoded vendors
Initialize basic x86 CPU information. It is safe to call this function multiple times.
Thermal Monitor and Clock Ctrl
Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
APIC on Chip
Advanced Vector Extensions 2
AVX-512 Byte and Word Instructions
AVX-512 Conflict Detection Instructions
AVX-512 Doubleword and Quadword Instructions
AVX-512 Exponential and Reciprocal Instructions
AVX-512 Foundation
AVX-512 Integer Fused Multiply-Add Instructions
AVX-512 Prefetch Instructions
AVX-512 Vector Bit Manipulation Instructions
AVX-512 Vector Length Extensions
Bit Manipulation Instruction Set 1
Bit Manipulation Instruction Set 2
Brand, e.g. Intel(R) Core(TM) i7-4770HQ CPU @ 2.20GHz.
Brand Index
Supports CET shadow stack features if 1.
Supports cache line demote if 1.
CLFLUSH line size Note: Value ∗ 8 = cache line size in bytes; used also by CLFLUSHOPT.
CLFLUSHOPT instruction
CLFLUSH instruction
CLWB instruction
Conditional Move/Compare Instruction
L1 Context ID
CMPXCHG8B Inst.
Direct Cache Access
Debugging Extensions
FPU CS and FPU DS values if 1.
Debug Store
CPL Qualified Debug Store
64-bit DS Area
Enhanced Intel SpeedStep® Technology
Extended Family ID
Extended Model ID
Family ID
x87 FPU Data Pointer updated only on x87 exceptions if 1.
Fused Multiply Add
x87 FPU on Chip
Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.
FXSAVE/FXRSTOR
Transactional Synchronization Extensions
Multi-threading
MSR is supported if 1.
Initial APIC ID
Intel Processor Trace.
If 1, supports INVPCID instruction for system software that manages process-context identifiers.
The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-bit mode.
Reports the maximum input value for supported leaf 7 sub-leaves.
Maximum Input Value for Basic CPUID Information
Maximum Input Value for Extended CPUID Information
Maximum number of addressable IDs for logical processors in this physical package.
Machine Check Architecture
Machine Check Exception
MMX Technology
Model
MONITOR/MWAIT
Supports MOVDIR64B if 1.
Supports MOVDIRI if 1.
Supports Intel® Memory Protection Extensions if 1.
RDMSR and WRMSR Support
Memory Type Range Registers
If 1, OS has set CR4.PKE to enable protection keys (and the RDPKRU/WRPKRU instructions).
Physical Address Extensions
Page Attribute Table
Pend. Brk. EN.
Process-context Identifiers
Carryless Multiplication
PCOMMIT instruction
Perf/Debug Capability MSR xTPR Update Control
PTE Global Bit
Memory Protection Keys for User-mode pages
PREFETCHWT1 instruction
Page Size Extensions
Page Size Extension
Processor Serial Number
RDPID and IA32_TSC_AUX are available if 1.
RDSEED instruction
Supports Intel® Resource Director Technology (Intel® RDT) Allocation capability if 1.
Supports Intel® Resource Director Technology (Intel® RDT) Monitoring capability if 1.
Transactional Synchronization Extensions
Self Snoop
SYSENTER and SYSEXIT
Supports Intel® Software Guard Extensions (Intel® SGX Extensions) if 1.
Supports SGX Launch Configuration if 1.
supports Intel® Secure Hash Algorithm Extens
Supports Supervisor-Mode Access Prevention (and the CLAC/STAC instructions) if 1.
Supports Supervisor-Mode Execution Prevention if 1.
Safer Mode Extensions
SSE Extensions
SSE2 Extensions
SSE3 Extensions
SSE4.1
SSE4.2
SSSE3 Extensions
Stepping ID
Enhanced REP MOVSB/STOSB if 1.
Therm. Monitor
Thermal Monitor 2
Time Stamp Counter
Processor Type, Specification: Intel
Supports user-mode instruction prevention if 1
Vendor, e.g. GenuineIntel.
VendorIndex encoded value.
VendorIndex name
Virtual machine
Virtual vendor, e.g. GenuineIntel or VMwareVMware.
VendorIndex encoded value for virtual machine.
Virtual-8086 Mode Enhancement
Virtual Machine Extensions
TPR Update Control
x86 CPU information
Basic information about CPU.
Extended information about CPU.
Common information for all x86 and x86_64 vendors.
$(GREEN This module is compatible with betterC compilation mode.)
Note: T.max value value is used to represent fully-associative Cache/TLB.
References: wikipedia:CPUID