XMM opcodes that conform to the following:
Generate two operand instruction with XMM 128 bit operands.
Unary SIMD instructions.
For instructions: CMPPD, CMPSS, CMPSD, CMPPS, PSHUFD, PSHUFHW, PSHUFLW, BLENDPD, BLENDPS, DPPD, DPPS, MPSADBW, PBLENDW, ROUNDPD, ROUNDPS, ROUNDSD, ROUNDSS
For instructions with the imm8 version: PSLLD, PSLLQ, PSLLW, PSRAD, PSRAW, PSRLD, PSRLQ, PSRLW, PSRLDQ, PSLLDQ
For "store" operations of the form: op1 op= op2 such as MOVLPS.
Load unaligned vector from address. This is a compiler intrinsic.
Emit prefetch instruction.
Emit prefetch instruction.
Store vector to unaligned address. This is a compiler intrinsic.
Create a vector type.
Builtin SIMD intrinsics