Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
Advanced Vector Extensions 2
AVX-512 Byte and Word Instructions
AVX-512 Conflict Detection Instructions
AVX-512 Doubleword and Quadword Instructions
AVX-512 Exponential and Reciprocal Instructions
AVX-512 Foundation
AVX-512 Integer Fused Multiply-Add Instructions
AVX-512 Prefetch Instructions
AVX-512 Vector Bit Manipulation Instructions
AVX-512 Vector Length Extensions
Bit Manipulation Instruction Set 1
Bit Manipulation Instruction Set 2
Supports CET shadow stack features if 1.
Supports cache line demote if 1.
CLFLUSHOPT instruction
CLWB instruction
FPU CS and FPU DS values if 1.
x87 FPU Data Pointer updated only on x87 exceptions if 1.
Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.
Transactional Synchronization Extensions
MSR is supported if 1.
Intel Processor Trace.
If 1, supports INVPCID instruction for system software that manages process-context identifiers.
The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-bit mode.
Supports MOVDIR64B if 1.
Supports MOVDIRI if 1.
Supports Intel® Memory Protection Extensions if 1.
If 1, OS has set CR4.PKE to enable protection keys (and the RDPKRU/WRPKRU instructions).
PCOMMIT instruction
Memory Protection Keys for User-mode pages
PREFETCHWT1 instruction
RDPID and IA32_TSC_AUX are available if 1.
RDSEED instruction
Supports Intel® Resource Director Technology (Intel® RDT) Allocation capability if 1.
Supports Intel® Resource Director Technology (Intel® RDT) Monitoring capability if 1.
Transactional Synchronization Extensions
Supports Intel® Software Guard Extensions (Intel® SGX Extensions) if 1.
Supports SGX Launch Configuration if 1.
supports Intel® Secure Hash Algorithm Extens
Supports Supervisor-Mode Access Prevention (and the CLAC/STAC instructions) if 1.
Supports Supervisor-Mode Execution Prevention if 1.
Enhanced REP MOVSB/STOSB if 1.
Supports user-mode instruction prevention if 1
Reports the maximum input value for supported leaf 7 sub-leaves